This invention relates to a semiconductor test system such as automatic test equipment (ATE) for testing semiconductor devices such as ICs and LSIs, and more particularly, to a single ATE system which behaves as multiple logic testers, each operating separately and asynchronously from the other, as well as a conventional single logic tester.
In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as automatic test equipment (ATE) or an IC tester, a semiconductor device to be tested is provided with test signals (patterns) at its appropriate pins with predetermined test timings. The semiconductor test system receives output signals from the device under test generated in response to the test signals. The output signals are sampled by strobe signals with specified timings to be compared with expected value signals to determine whether the semiconductor device under test performs the intended functions correctly or not.
FIG. 1 is a schematic block diagram showing an example of a conventional semiconductor test system. In the semiconductor test system of FIG. 1, a pattern generator 12 receives test data from a test processor 11. The pattern generator 12 generates a test pattern data to be provided to a wave formatter 14 and an expected value pattern to be provided to a pattern comparator 17. A timing generator 13 generates timing signals to synchronize the operation of the overall test system. In FIG. 1, the timing signals are provided, for example, to the pattern generator 12, the pattern comparator 17, the wave formatter 14, and an analog comparator 16.
The timing generator 13 also provides a test cycle (tester rate) pulse and timing data to the wave formatter 14. The pattern (test vector) data defines xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, i.e., rising and falling edges of the test signal waveform. The timing data (timing set data) defines timings (delay times) of the rising and falling edges of the waveform relative to the test cycle pulse. Typically, the timing data also includes waveform information such as an RZ (return to zero), NRZ (non-return to zero) or EOR (exclusive OR) waveform.
Based on the pattern data from the pattern generator 12 and the test cycle pulse and timing data from the timing generator 13, the wave formatter 14 forms a test signal having specified waveforms and timings. The wave formatter 14 sends the test signal to the DUT 19 through a driver 15. The wave formatter 4 includes set/reset flip-flops (not shown) to form the test signal to be provided to the driver 15. The driver 15 regulates the amplitude, impedance, and/or slew rate of the test signal and applies the test signal to the DUT 19.
A response signal from the DUT 19 is compared with a reference voltage at a predetermined strobe timing by the analog comparator 16. The resultant logic signal is provided to the pattern comparator 17 wherein a logic comparison is performed between the resultant logic pattern from the analog comparator 16 and the expected value pattern from the pattern generator 12. The pattern comparator 17 checks whether two patterns match with each other or not, thereby determining pass or failure of the DUT 19. When a failure is detected, such failure information is provided to a fail memory 18 and is stored along with the information of the failure address of the DUT 19 from the pattern generator 12 in order to perform failure analysis.
In the conventional test system, however, either in the per-pin or pin cluster architecture, the test pins are treated as a single group of pins that start and run together until the completion of the test program. In other words, these conventional test systems perform the parallel testing by duplicating the same test pattern across a single pattern memory. Thus, the above noted operation has the restriction that each device is running the same test pattern and the pattern on each device must run to completion even when an error in one of the DUTs is detected.
A pin-cluster tester refers to a semiconductor test system wherein tester resources such as a timing generator and reference voltages are commonly used for all or predetermined number of test channels (test pins). An IC tester having the shared resource (cluster-pin) structure such as shown in FIG. 1 is considered economical but not flexible enough to test recent IC devices with high complexity and high speed. Compared to the shared resource tester that shares the test parameters for each terminal pin of the DUT, the per-pin tester is better suited for testing high speed LSIs since a complex test pattern and timing can be generated more freely since it can produce the test parameters for each terminal pin of the DUT independently from the other pins. In a typical per-pin IC tester, the timing generator 13 and wave formatter 14 in FIG. 1 are separately provided to each test pin, i.e., to each terminal pin of the DUT.
In the semiconductor test industry, there is a need to test multiple devices in parallel to improve test efficiency. There are semiconductor test systems that can test multiple devices in parallel. FIGS. 2A and 2B show examples of basic configuration for testing a plurality of semiconductor devices at the same time. In FIG. 2A, two test heads TH1 and TH2 are connected to automatic test equipment (ATE) 10 to test two devices DUT1 and DUT2 in parallel. In FIG. 2B, two devices DUT1 and DUT2 are tested on a single test head TH connected to the ATE 10.
In the conventional test system, however, either in the per-pin or pin cluster architecture, the test pins are treated as a single group of pins that start and run together until the completion of the test program. In other words, these conventional test systems perform the parallel testing by duplicating the same test pattern across a single pattern memory. Thus, the above noted operation has the restriction that each device is running the same test pattern and the pattern on each device must run to completion even when an error in one of the DUTs is detected.
Therefore, it is an object of the present invention to provide a semiconductor test system which functions as multiple logic testers where each logic tester operates independently and asynchronously from the other.
It is another object of the present invention to provide a semiconductor test system which behaves as multiple logic testers where each logic tester is freely configured in terms of test pins corresponding to requirements of a semiconductor device to be tested.
It is a further object of the present invention to provide a semiconductor test system which is capable of conducting either synchronous or asynchronous parallel testing on multiple devices.
It is a further object of the present invention to provide a semiconductor test system which is capable of running a plurality of test programs in parallel and simplifying software programming for multiple device parallel testing.
It is a further object of the present invention to provide a semiconductor test system which supports virtual multiple logic testers with low cost and high test flexibility and test efficiency.
According to the present invention, the semiconductor test system is comprised of a host computer controlling an overall operation of a semiconductor test system by executing a test program, a plurality of pin-units each having means for generating a test pattern to a assigned pin of a semiconductor device under test (DUT) and evaluating a resultant response of the DUT, a pin-unit bus provided between said host computer and the plurality of pin-units for transmitting data, address, control signals and clocks, and means for configuring the pin-units corresponding to input/output pins of devices under test when a single or group selection address is placed on the pin-unit bus by the host computer.
In the test system of the present invention which supports multiple virtual testers, groups of test pins are dynamically allocated to separate devices under test (DUTs) or separate subsystems of system-on-a-chip (SoC). These groups are addressed by the tester hardware separately and treated as discrete individual test systems. The group allocation and selection is accomplished through a hardware mechanism that allows the host computer to write the group selection address (GSA) on the pin-unit bus. Tests running on these virtual testers can be started together or separately and end independently. Thus, the present invention allows to test a plurality of different IC devices simultaneously on a single test system. The concept of the present invention is applicable to either the tester per-pin architecture or the pin-cluster architecture.